1. Field of the Invention
The present invention relates to a gate stack, and more particularly to a CMOS gate stack with a high dielectric constant gate dielectric and integrated diffusion barrier.
2. Description of the Related Art
Beyond the 100 nm CMOS technology node, device scaling has been difficult and is now believed to require the introduction of new insulators into the gate stack.
That is, previously, the incorporation of nitrogen into SiO2 gate dielectrics has been attempted to reduce dopant diffusion. In this case, the prevalent method to form the structure has been thermal processing in O2, N2O, and NO gases. By varying the sequence of gases, structures with different nitrogen profiles (e.g., near top, near bottom) can be manufactured. Also, nitrogen implantation into the Si substrate prior to thermal oxidation has been used.
Oxide/nitride stacks have also been used where the nitride has been deposited onto a thermally grown oxide. However, the methods to form the structures have been problematic in most cases. Indeed, thermal processing in N2O, NO gas may not be possible for many of the materials currently contemplated because of thermal budget constraints.
Thus, beyond the 100 nm CMOS technology node, device scaling requires the introduction of new insulators into the gate stack and a new methodology. These materials, generally referred to as “high-K” dielectrics, should have a dielectric constant which is larger than that of conventional SiO2 gate oxide, and more specifically a insulation constant (permittivity) which is in a range of approximately 4 to 100. These high-K dielectrics include binary metal oxides such as Al2O3, HfO2, ZrO2, TiO2, La2O3, Y2O3, Gd2O3, Ta2O5, and their silicates and aluminates. It is noted that the term “high-K dielectrics” refers to materials having a greater permittivity of the material (e.g., a greater insulation characteristic).
In CMOS devices, the high-K dielectric electrically separates the heavily (n or p-type) doped poly-Si or the metal gate from the active region (channel) of the device.
Device fabrication and operation require gate dielectric robustness with respect to thermal reactions between the poly-Si (or metal) gate and the high-K layer, resistance to dopant (e.g. B, P, As, etc.) or metal diffusion from the gate, and resistance to moisture or oxygen diffusion through the gate dielectric to prevent oxidation of the silicon near the active region of the device.
However, prior to the invention, no such method and structure has been developed providing such gate dielectric robustness. That is, while there are some high K gate dielectrics that are being developed, no robustness has been shown thereby. Indeed, work has been performed on such dielectrics by attempting to add some resistance to such dielectrics either by adding something on the dielectric layer or spreading some material through the layer or by incorporating nitrogen or the like into the layer. Indeed, the conventional methods have focused on either using silicon dioxide and nitrogen in the gate dielectric. Another method has attempted to incorporate aluminum nitride into the gate dielectric layer.
However, again, not robustness has been shown by such method, as would be advantageous as discussed above.